Multi-layer wiring technology has become increasingly more important in semiconductor device industries in forming integrated circuits (ICs) and large-scale integrated circuits (LSIs) in order to allow for high density integration and a great freedom for electric connection of the elements in these ICs and LSIs. In fact, as the dimensions of the elements of a chip are reduced to increase their density on a given substrate, lead lines tend to occupy a large percentage of the total area available on the chip, which sometimes amounts to as much as 20-30 percent of the total areas. However, the widths of the lead lines cannot be decreased arbitrarily because lead lines are required to have sufficient current capacities or are limited electric resistance below a required level. Thus, a multi-level lead line structure is a very promising solution to this problem.
The advantage of the multi-level lead line structure apparently lies in the fact that that it does not require wiring spaces between the elements on an IC chip, thereby increasing the density of the elements on the chip and minimizing the total size of the chip. The multi-level lead line structure may also increase a freedom in patterning the lead lines and hence provide ease of setting up the lead lines satisfying electric capacity-resistance requirements.
FIG. 1 illustrates in step a typical procedure for manufacturing the most fundamental multi-level lead line structure, i.e. a double-layer lead line structure. In step S01 a substrate having thereon semiconductor elements is provided. Contact holes for connection of the elements with first level lead lines are formed in the substrate.
In step S02 a first metal layer is formed for the first level lead lines. Typically, aluminum or aluminum alloy is used for the metal layer, but other metals such as copper (Cu), molybdenum (Mo), tungsten (W), silicide, titanium (Ti), paradium (Pd), platinum (Pt), and gold (Au) may be used equally well for the metal layer as needed.
In step S03 the first metal layer is processed by a known lithographic method, resulting in the first level lead lines. The first level lead lines may be alternatively formed by providing appropriated metal lead wires without using a lithographic method.
In step S04, a first insulation layer is formed on the first level lead lines. If the first metal layer is aluminum, SiO.sub.2 is the best insulating material from the point of amenity with the aluminum lead lines. Although sputtering methods were popular in the formation of insulating oxide layers in early stages of the development of multi-layered LSIs, it is now customary to use a low-temperature CVD method using SiH.sub.4 in the formation of oxide layers. Phosphorous glass (PSG) and plasma Si.sub.3 N.sub.4 are also commonly used.
In step S05, via holes are formed in the first insulation layer.
In step S06, a second metal layer is formed for second level lead lines, using essentially the same material as for the first metal layer.
In step S07, the second metal layer is patterned and processed by a known lithographic technique to form the second level lead lines.
In step S08, a second insulation layer is formed on the second level lead lines such that the insulation layer provides passivation function. The second insulation layer is made of essentially the same material as the first insulation layer.
In step S09, appropriate bonding pads are formed in accordance with the wiring technique used.
The steps SO1 through SO9 as shown in FIG. 1 provide a double layer lead line structure. In the case of a three-layer lead line structure, the step S05 for forming via holes through the step S08 for forming a further insulation layer are repeated for the third level lead lines.
The metal layers are required to have such material properties as ability to provide sufficient step coverage, low resistivity, good ohmic contact with silicon and aluminum, adhesivity to an underlying insulation layer of SiO.sub.2, ease of lithographic processing, uniformity and homogeneity when formed in the form of a thin layer, and chemical and thermal stabilities that may prevent electromigration.
The insulation layers are required to have such properties as ability to provide sufficient step coverage, high electric insulation, adhesivity to metals, inertness to metals, ease of lithographic processing, homogeneity and uniformity when formed in the form of a thin layer, having little pin-holes and cracks, chemical and thermal stabilities, ease of low-temperature deposition, and good passivation characteristic against any contamination.
In steps S03 and S07, the first and the second metal layers of aluminum or aluminum alloy are fabricated to form the first and the second level high density lead lines, respectively, by irradiating light beams on the photoresists to harden or dissolve the photoresists. The light beams, however, can be reflected by the respective underlying metal layers and further harden or dissolve the photoresists, which makes it difficult to carry out fine patterning of the metal layers for the lead lines.
Therefore, in order to prevent such reflection of light, each of the metal layers is generally applied thereto with an anti-reflective film, which is typically TiN (hereinafter referred to as anti-reflective TiN or ARC-TiN). Steps S02 and S07 for forming metal layers and subsequent steps for forming ARC-TiN layers as shown in FIG. 1 are carried out continuously in an evacuated chamber.
In order to meet growing demands for highly integrated, high-density semiconductor devices, requirements for fabricating a multi-level lead line structure have become more stringent. The requirements include sufficiency of step coverage of via holes (contact holes) having high aspect ratio (which is defined by a ratio of transverse size to the longitudinal size of a via hole). In order to provide sufficient step coverage of via holes, it is necessary to grow the metal layer at a temperature at about 400.degree. C. or higher so that the aluminum or aluminum alloy layer maintains sufficient fluidity for the coverage.
However, if the temperature of 400.degree. C. or higher is maintained while depositing the anti-reflective TiN layer, a problematic ring shaped etch residues result. This is because the metal layers and the anti-reflective TiN layers have different thermal expansion coefficients. For example, aluminum has a thermal expansion coefficient of 2.3.times.10.sup.-5 /deg at 293.degree. K., which is greater than the thermal expansion coefficient, 0.7.times.10.sup.-5 /deg, of TiN. As a consequence, if the metal layers and the anti-reflective TiN are formed at 400.degree. C. or above and then cooled to a room temperature, cracks will be generated in the TiN layer due to larger contraction of the metal layer than that of the anti reflective layer. When the anti-reflective TiN layer is then patterned and etched, the cracks will result in ring shaped faults on the substrate, as described below.
This ring shaped fault problem has been discussed by I. G. Colgan et al. in detail in Proc. 11th VMCC Conf., pp. 284-286, June 1994, which is hereby incorporated by reference into this disclosure.
It is shown in FIG. 2A that a metal layer consisting of Ti/AlCu(Aluminum alloy)/Ti (referred to as "TAC structure") is provided on an underlayer of SiO.sub.2. The metal layer is formed by sequentially depositing a Ti layer, an Al alloy layer such as AlCu, and another Ti layer at an elevated temperature. Because of the elevated temperature, Aluminum has relatively large grains.
As shown in FIG. 2B, the deposition of the Al alloy is followed by the deposition of an ARC-layer of TiN, which is subsequently cooled to a room temperature. In this case, since there is a tensile stress in the Al alloy layer, the ARC-TIN layer on the Al alloy layer is cracked due to grain collapse under the tensile stress, result in grooves or holes in the ARC-TiN layer.
In the next step, the substrate is subjected to a sequence of lithographic processes which includes application of a photoresist onto the ARC-TiN layer, irradiation of light, development, and rinsing, as shown in FIG. 2C. The development is done by a developing liquid such as TMAH (tetramethylammoniumhalide). The TMAH will infiltrate into the holes in the ARC-TiN and etches the aluminum alloy, so that Al.sub.2 O.sub.3 (alumina) is formed in the subsequent rinse process.
In the etching process as shown in FIG. 2D, the Al.sub.2 O.sub.3 works as an etching mask to leave ring shaped etch residues of Al alloy. The size of such a ring shaped etch residue depends on the development time and the size of the hole, with a larger etch residue for a longer development time and for a larger hole. Such ring shaped residues result in ring faults of lead lines.
Therefore, in order to prevent the ring faults arising from the cracks due to mismatch of thermal expansion coefficients of the Al alloy layer and the ARC-TiN layer, it is necessary to form the ARC-TiN layer at or below 150.degree. C. after the formation of the Al alloy layer at or above 400.degree. C.
However, if the anti reflective layer of TiN is deposited on the Al alloy layer at or below 150.degree. C. immediately after the deposition of the Al alloy layer at or above 400.degree. C., the underlying Al alloy layer is rapidly cooled to shrink, thereby generating grain boundaries in the Al alloy layer.
By grain boundaries we mean interfaces between individual crystalline structures (crystalline grains) in a solid. Metals such as aluminum may have crystalline structures which are defined precisely in terms of three dimensional periodic arrangement of atoms (or ions). The direction of a crystalline structure is characterized by a set of crystal axes. The individual crystalline grains have the same crystalline structure, but their crystal axes are oriented in different directions. Thus, the grain boundaries may be viewed as lattice imperfections that appear in the form of interfaces between two neighboring crystals.
If the grain boundaries are formed by quick thermal contraction of the Al alloy layer, deep grooves are formed in the surface of the Al alloy along the grain boundaries. Since the ARC-TIN layer is then formed over the Al alloy surface having such deep grooves, the surface of the TiN layer has extremely poor flatness. That is, the TiN layer has discontinuities. If such TiN layer is lithographically processed, the TiN layer is patterned in an undesirable configuration, leaving etch residues at the discontinuities and the grain boundaries, which cause insufficient insulation in the underlying lead lines.
As described above, the deposition of the ARC-TiN layer at the same high temperature as the deposition of the metal layer such as aluminum or aluminum alloy entails an impediment of ring shaped faults caused by cracks and holes. If, on the other hand, the ARC-TIN layer is deposited at a lower temperature in an attempt to overcome this problem, the Aluminum or Aluminum alloy layer is rapidly cooled and suffers from grooves in the layer and surface discontinuities, which in turn result in etch residues and undesirable patterns of the underlying layer as mentioned above and hence unsatisfactory insulation of the lead lines.